The A4 and the A8: secrets of the iPad’s brain

Most companies, when they go to the enormous expense of designing a complex chip, tell everyone about it. Even a company like Sun or IBM, whose chips are used only in their own computers, unveil the details of their new processors well before products based on those new parts come to market. This is true for game consoles, for SoCs of all flavors, for PC chips, and for most of the rest of the semiconductor industry. It's not, however, true for Apple.

Since the unveiling of the iPad last month, all the public has learned about the application processor that powers the device is a two-letter name: A4. The rest of the details have been treated as Top Secret, and this secrecy has stoked plenty of speculation, some of it reasonable and some of it completely and totally unhinged.

Why has Apple been so secretive about the A4? Why hasn't the company presented a paper on the device at ISSCC, or published a whitepaper?

I don't know the answer to these questions, but given what I do know about the A4, I suspect that the reason is twofold. First—and this is purely my supposition—Steve Jobs just loves secrets. The A4 no doubt gives him that special, "I have my very own custom SoC that you don't know anything about" feeling, and if we're honest with ourselves, wouldn't we all love to know what it's like to have that feeling? I know I would.

The second, and perhaps most likely reason behind Apple's silence, is that the A4 just isn't anything to write home about—and on this second point, I actually know a thing or two. If Apple were to tell you what's in the A4, most of the focus would be on what the chip is not, rather than on what the iPad is.

Meet the A4

As I watched the videos and read the reports of the iPad in action at the launch event, I was thoroughly convinced that the device was built on the out-of-order Cortex A9, possibly even a dual-core version. But it turns out that the the A4 is a 1GHz custom SoC with a single Cortex A8 core and a PowerVR SGX GPU. The fact that A4 uses a single A8 core hasn't been made public, but I've heard from multiple sources who are certain for different reasons that this is indeed the case. (I wish I could be more specific, but I can't.)

In all, the A4 is quite comparable to the other Cortex A8-based SoCs that are coming onto the market, except that the A4 has even less hardware. The iPad doesn't have much in the way of I/O, so the A4 itself can do away with the I/O that it doesn't need. In contrast, the typical Cortex A8-based SoC has more I/O hardware than a mobile phone can use, because you never know what customers will need which interface types.

For instance, an A8-based SoC like the Freescale i.MX51 shown above has an infrared block, three UART blocks for serial communication (RS232 and the like), four USB blocks, and a keypad controller, to name just a few. Of these, the iPad probably needs only one USB port and one UART for serial connections, both of which are wired to the 30-pin connector (assuming that this is the same 30-pin connector as the iPhone). The multitouch input controller will interface with the chip via either a USB port or a serial port (I looked at the datasheet for the STM32TS60, which can do either USB or serial), so perhaps there's another port for that purpose.

Apple's 30-pin connector supports TV-out, but no external display attachment has been announced for the device, so it's possible that the SoC forgoes the common TV-out I/O block and related support for a secondary display. (It has video out. Apologies for missing this detail.)

Another common SoC set of blocks that the A4 probably does without are related to still and video camera support. Apple's iPad may well be the only Cortex A8-device to come to market without any type of camera built in, so Apple has probably ditched some dedicated image processing blocks.

While it's fun to speculate about what Apple didn't include in the A4, the ultimate point is this: with one 30-pin connector on the bottom and no integrated camera of any kind, the A4 needs a lot less in the way of I/O support than comparable chips that are intended for smartphones or smartbooks. This means that the A4 is just a GPU, a CPU, memory interface block (NAND and DDR), possibly security hardware, system hardware, and a few I/O controllers. It's lean and mean to a degree that isn't possible with an off-the-shelf SoC.

What was the role of P.A. Semi?

So if Apple just licensed the A8 and didn't design a custom CPU core, then what was the point of the P.A. Semi acquisition? The answer to this question is still unclear.

Apple bought P.A. Semi in late April 2008. A little over a year isn't near enough time to do a new core design around the ARMv7 architecture. Something like Qualcomm's Scorpion core, which is a custom implementation of ARM v7 that's comparable to the A8, but with a wider SIMD engine and a deeper pipeline, was a multiyear project. I could easily imagine that Apple is working on something comparable to Scorpion, but this wouldn't be ready for a while.

If they were involved at all in the A4 design, and it's still not 100 percent clear that they were, it's likely that the P.A. Semi team made its biggest contribution to the A4 in the area of dynamic power optimization.

The PWRficient chip that the P.A. Semi team unveiled in late 2005 achieved miraculous levels of efficiency through pervasive use of power and clock gating. Power gating is a relatively straightforward technique that involves shutting down the parts of a chip that aren't in use. It's harder to implement in practice than it sounds, though, because you have to divide the chip up into blocks that can be put to sleep and awakened independently. You also have to size and arrange those blocks so that the extra delay involved in entering and exiting sleep states doesn't screw up the chip's overall timing. These delay and timing issues make power gating hard to implement in high-speed processors, which is why the amount of power gating that the PWRficient processor used was remarkable for a high-performance processor.

Clock gating is the other technique that PWRficient used extensively, and it also comes with its own challenges. The clock distribution network can account for up to half the dynamic power draw in a modern SoC. Clock gating is a method for pruning the clock tree by cutting off the clock to parts of the chip that don't need it at a particular moment.

The exact degree to which the A4 uses either of these two techniques won't be clear until Apple does a big reveal, and that may not ever happen. But even if they're not extensively used in the current A4, these techniques are very likely to be a larger part of future iterations or variants of the processor.