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GPCE 2019
Sun 20 - Fri 25 October 2019 Athens, Greece
co-located with SPLASH 2019

In modern runtime systems, memory layout calculations are hand-coded in low-level systems languages. The primitives in these languages are not powerful enough to describe a rich set of layouts, leading developers to rely on ad-hoc macros as well as numerous interrelated static constants and other boilerplate code. A memory management policy must also carefully orchestrate all the different address calculations to modify memory cooperatively, a task ill-suited to the low-level systems languages at hand which do not provide the proper safety mechanisms.

In this paper we introduce Floorplan, a declarative language for specifying memory layouts at a high level. Constraints formerly implemented by describing how to compute locations are, in Floorplan, defined declaratively using explicit layout constructs. The challenge here was to discover layout constructs capable of sufficiently and soundly enabling the automatic generation of address calculations, including code deemed unsafe according to the memory safety paradigm of Rust. Floorplan is implemented as a compiler for generating a Rust library from a Floorplan specification. In a case study of an existing implementation of the immix garbage collection algorithm, Floorplan eliminates 55 out of the 63 unsafe lines of code: 100% of the unsafe lines of code pertaining to memory safety.

Tue 22 Oct

Displayed time zone: Beirut change

11:00 - 12:30
Domain-specific languages and modelingGPCE 2019 at Ground floor conference room
Chair(s): Ulrik Pagh Schultz University of Southern Denmark
11:00
30m
Talk
Automated Metamodel Augmentation for Seamless Model Evolution Tracking and Planning
GPCE 2019
Michael Nieke TU Braunschweig, Germany, Adrian Hoff TU Braunschweig, Christoph Seidl Technische Universität Braunschweig
11:30
30m
Talk
Floorplan: Spatial Layout in Memory Management SystemsDistinguished Paper Award
GPCE 2019
Karl Cronburg Tufts University, Sam Guyer Tufts University
DOI Pre-print
12:00
20m
Talk
Compiler Generation for Performance-Oriented Embedded DSLs (Short Paper)
GPCE 2019
Amir Shaikhha University of Oxford, Vojin Jovanovic Oracle Labs, Christoph E. Koch EPFL